-- alu.vhd 
-- my-arm processor ALU
-- Oleg Gavrilchenko
-- reffum@bk.ru

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;

entity alu is
port(
   i_a, i_b       : in std_logic_vector(C_BUS_WIDTH - 1 downto 0);
   i_carry        : in std_logic;
   i_function     : in alu_functions;
   
   o_out          : out std_logic_vector(C_BUS_WIDTH - 1 downto 0);
   o_flags        : out status_flags
   );
end entity alu;

architecture imp of alu is
begin
   o_out <= (others => '0');
   o_flags <= (others => '0');
   -- Naive implementation
   
end architecture;
